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connection diagram 8-pin plastic mini-dip (n) and soic (r) packages null ?n +in output null 1 2 3 4 8 7 6 5 ? s top view +v s ad817 nc nc = no connect rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a high speed, low power wide supply range amplifier ad817 ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features low cost high speed 50 mhz unity gain bandwidth 350 v/ m s slew rate 45 ns settling time to 0.1% (10 v step) flexible power supply specified for single (+5 v) and dual ( 6 5 v to 6 15 v) power supplies low power: 7.5 ma max supply current high output drive capability drives unlimited capacitive load 50 ma minimum output current excellent video performance 70 mhz 0.1 db bandwidth (gain = +1) 0.04% & 0.08 8 differential gain & phase errors @ 3.58 mhz available in 8-pin soic and 8-pin plastic mini-dip product description the ad817 is a low cost, low power, single/dual supply, high speed op amp which is ideally suited for a broad spectrum of signal conditioning and data acquisition applications. this breakthrough product also features high output current drive capability and the ability to drive an unlimited capacitive load while still maintaining excellent signal integrity. the 50 mhz unity gain bandwidth, 350 v/ m s slew rate and set- tling time of 45 ns (0.1%) make possible the processing of high speed signals common to video and imaging systems. further- more, professional video performance is attained by offering dif- ferential gain & phase errors of 0.04% & 0.08 @ 3.58 mhz and 0.1 db flatness to 70 mhz (gain = +1). the ad817 is fully specified for operation with a single +5 v power supply and with dual supplies from 5 v to 15 v. this power supply flexibility, coupled with a very low supply current of 7.5 ma and excellent ac characteristics under all power sup- ply conditions, make the ad817 the ideal choice for many de- manding yet power sensitive applications. in applications such as adc buffers and line drivers the ad817 simplifies the design task with its unique combination of a 50 ma minimum output current and the ability to drive unlimited capacitive loads. the ad817 is available in 8-pin plastic mini-dip and soic packages. ordering guide temperature package package model range description option AD817AN C40 c to +85 c 8-pin plastic dip n-8 ad817ar C40 c to +85 c 8-pin plastic soic r-8 7 6 3 2 +v s 4 tektronix p6201 fet probe hp pu lse generator ad817 1k w 50 w 1k w c l 1000pf v out 0.01 m f 3.3 m f ? s v in 0.01 m f 3.3 m f 10 90 100 0% 5v 500ns 100pf load 1000pf load ad817 driving a large capacitive load
ad817Cspecifications rev. a C2C (@ t a = +25 8 c, unless otherwise noted) ad817a parameter conditions v s min typ max units dynamic performance unity gain bandwidth 5 v 30 35 mhz 15 v 45 50 mhz 0, +5 v 25 29 mhz bandwidth for 0.1 db flatness gain = +1 5 v 18 30 mhz 15 v 40 70 mhz 0, +5 v 10 20 mhz full power bandwidth 1 v out = 5 v p-p r load = 500 w 5 v 15.9 mhz v out = 20 v p-p r load = 1 k w 15 v 5.6 mhz slew rate r load = 1 k w 5 v 200 250 v/ m s gain = 1 15 v 300 350 v/ m s 0, +5 v 150 200 v/ m s settling time to 0.1% C2.5 v to +2.5 v 5 v 45 ns 0 vC10 v step, a v = C1 15 v 45 ns settling time to 0.01% C2.5 v to +2.5 v 5 v 70 ns 0 vC10 v step, a v = C1 15 v 70 ns total harmonic distortion f c = 1 mhz 15 v 63 db differential gain error ntsc 15 v 0.04 0.08 % (r load = 150 w ) gain = +2 5 v 0.05 0.1 % 0, +5 v 0.11 % differential phase error ntsc 15 v 0.08 0.1 degrees (r load = 150 w ) gain = +2 5 v 0.06 0.1 degrees 0, +5 v 0.14 degrees input offset voltage 5 v to 15 v 0.5 2 mv t min to t max 3mv offset drift 10 m v/ c input bias current 5 v, 15 v 3.3 6.6 m a t min 10 m a t max 4.4 m a input offset current 5 v, 15 v 25 200 na t min to t max 500 na offset current drift 0.3 na/ c open loop gain v out = 2.5 v 5 v r load = 500 w 2 4 v/mv t min to t max 1.5 v/mv r load = 150 w 1.5 3 v/mv v out = 10 v 15 v r load = 1 k w 4 6 v/mv t min to t max 2.5 5 v/mv v out = 7.5 v 15 v r load = 150 w (50 ma output) 2 4 v/mv common-mode rejection v cm = 2.5 v 5 78 100 db v cm = 12 v 15 v 86 120 db 15 v 80 100 db power supply rejection v s = 5 v to 15 v 75 86 db t min to t max 72 db input voltage noise f = 10 khz 5 v, 15 v 15 nv/ ? hz input current noise f = 10 khz 5 v, 15 v 1.5 pa/ ? hz
ad817a parameter conditions v s min typ max units input common-mode 5 v +3.8 +4.3 v voltage range C2.7 C3.4 v 15 v +13 +14.3 v C12 C13.4 v 0, +5 v +3.8 +4.3 v +1.2 +0.9 v output voltage swing r load = 500 w 5 v 3.3 3.8 v r load = 150 w 5 v 3.2 3.6 v r load = 1 k w 15 v 13.3 13.7 v r load = 500 w 15 v 12.8 13.4 v r load = 500 w 0, +5 v +1.5, +3.5 v output current 15 v 50 ma 5 v 50 ma 0, +5 v 30 ma short-circuit current 15 v 90 ma input resistance 300 k w input capacitance 1.5 pf output resistance open loop 8 w power supply operating range dual supply 2.5 18 v single supply +5 +36 v quiescent current 5 v 7.0 7.5 ma t min to t max 5 v 7.5 ma 15 v 7.5 ma t min to t max 15 v 7.0 7.5 ma notes 1 full power bandwidth = slew rate/2 p v peak . specifications subject to change without notice. ad817 rev. b C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 plastic (n) . . . . . . . . . . . . . . . . . . . . . . see derating curves small outline (r) . . . . . . . . . . . . . . . . . see derating curves input voltage (common mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . 6v output short circuit duration . . . . . . . . see derating curves storage temperature range n, r . . . . . . . . . C65 c to +125 c operating temperature range . . . . . . . . . . . . C40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-pin plastic package: q ja = 100 c/watt; 8-pin soic package: q ja = 160 c/watt. maximum power dissipation ?watts ambient temperature ? c 2.0 1.5 0 ?0 90 ?0 ?0 ?0 ?0 0 10 20 30 50 60 70 80 40 1.0 0.5 8-pin mini-dip package 8-pin soic package t j = +150 c maximum power dissipation vs. t emperature warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad817 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. b C4C ad817Ctypical characteristics 20 0 15 5 10 020 51015 input common-mode range ? volts supply voltage ? volts ? cm +v cm figure 1. common-mode voltage range vs. supply 20 0 15 5 10 020 51015 supply voltage ? volts output voltage swing ? volts r l = 500 w r l = 150 w figure 2. output voltage swing vs. supply v s = 15v 10k 100 10 1k 30 0 15 5 10 20 25 load resistance ? w output voltage swing ?volts p-p v s = 5v figure 3. output voltage swing vs. load resistance -40 c 8.0 6.0 7.5 6.5 7.0 020 51015 supply voltage ? volts quiescent supply current ?ma +25 c +85 c figure 4. quiescent supply current vs. supply voltage for various temperatures slew rate ?v/ m s 20 5 015 10 supply voltage ? volts 200 300 350 400 250 figure 5. slew rate vs. supply voltage 1k 10k 100m 10m 1m 100k 100 1 0.01 0.1 10 frequency ?hz closed-loop output impedance ?ohms figure 6. closed-loop output impedance vs. frequency
ad817 rev. b C5C 7 1 4 2 3 6 5 140 ?0 ?0 120 80 60 40 100 20 0 ?0 temperature ? c input bias current ? m a figure 7. input bias current vs. temperature 130 30 90 50 70 110 140 ?0 ?0 120 100 80 60 40 20 0 ?0 temperature ? c short circuit current ?ma source current sink current figure 8. short circuit current vs. temperature 100 20 80 40 60 ?0 140 ?0 100 120 80 60 40 20 0 ?0 temperature ? c phase margin ?degrees phase margin gain bandwidth 20 80 40 60 unity gain bandwidth ?mhz figure 9. unity gain bandwidth and phase margin vs. temperature 100 ?0 40 0 20 80 60 1g 10k 1k 100m 10m 1m 100k frequency ?hz +100 +40 0 +20 +80 +60 phase margin ?degrees open-loop gain ?db gain 15v supplies gain 5v supplies phase 5v or 15v supplies r l = 1k w figure 10. open-loop gain and phase margin vs. frequency 100 1k 10k 7 4 1 2 3 5 6 load resistance ?ohms open-loop gain ?v/mv 15v 5v figure 11. open loop gain vs. load resistance 100 10 30 20 40 50 60 70 80 90 100m 1k 100 10m 1m 100k 10k frequency ?hz psr ?db positive supply negative supply figure 12. power supply rejection vs. frequency
rev. b C6C ad817Ctypical characteristics 120 40 100 60 80 1k 10m 10k 100k 1m frequency ?hz cmr ?db figure 13. common-mode rejection vs. frequency 100k 1m 100m 10m frequency ?hz output voltage ?volts p-p r l = 1k w r l = 150 w 30 10 0 20 figure 14. large signal frequency response 10 ?0 ? ? ? 2 ? 0 4 6 8 160 20 0 140 120 100 80 60 40 settling time ?ns output swing from 0 to v 0.1% 1% 1% 0.01% 0.1% 0.01% figure 15. output swing and error vs. settling time ?0 ?00 ?0 ?0 ?0 ?0 ?0 10m 1k 10 0 1m 100k 10k frequency hz harmonic distortion db v in = 1v p-p gain = +2 2nd harmonic 3rd harmonic figure 16. harmonic distortion vs. frequency 50 0 30 10 20 40 10m 10 31m 100k 10k 1k 100 frequency ?hz input voltage noise ?nv/ hz figure 17. input voltage noise spectral density 380 300 360 320 340 ?0 140 ?0 100 120 80 60 40 20 0 ?0 temperature ? c slew rate ?v/ m s figure 18. slew rate vs. temperature
ad817 rev. b C7C supply voltage ?volts 0.05 0.03 0.04 differential phase ?degrees differential gain ?percent 0.04 0.1 0.06 0.08 15 5 10 diff gain diff phase figure 19. differential gain and phase vs. supply voltage frequency ?hz gain db 100k 1m 100m 10m 5 0 ? ? ? ? ? 1 2 3 4 v s = 5v v s = +5v v s = 15v v s 15v 5v +5v c c 3pf 4pf 6pf 0.1db flatness 16mhz 14mhz 12mhz v out v in 1k w 1k w c c figure 20. closed-loop gain vs. frequency, gain = C1 frequency ?hz gain db 100k 1m 100m 10m 5 0 ? ? ? ? ? 1 2 3 4 v s = 5v v s = +5v v s = 15v v s 15v 5v +5v 0.1db flatness 70mhz 26mhz 17mhz v out v in 1k w 150 w figure 21. closed-loop gain vs. frequency, gain = +1 +v s tektronix p6201 fet probe hp pulse (ls) or function (ss) generator 100 w 50 w 1k w r l v out 0.01 m f 3.3 m f ? s v in tektronix 7a24 pr ea mp ad817 7 6 3 2 4 0.01 m f 3.3 m f figure 22. noninverting amplifier connection 10 90 100 0% 50ns 5v 5v figure 23. noninverting large signal pulse response, r l = 1 k w 10 90 100 0% 20ns 200mv 200mv figure 24. noninverting small signal pulse response, r l = 1 k w
rev. b C8C ad817Ctypical characteristics 10 90 100 0% 5v 50ns 5v figure 25. noninverting large signal pulse response, r l = 150 w 10 90 100 0% 20ns 200mv 200mv figure 26. noninverting small signal pulse response, r l = 150 w r in 1k w +v s tektronix p6201 fet pr obe hp pulse (l sig ) or function (s sig ) generator 50 w 1k w r l v out 0.01 m f 3.3 m f ? s v in tektronix 7a24 preamp ad817 7 6 3 2 4 0.01 m f 3. 3 m f figure 27. inverting amplifier connection 10 90 100 0% 5v 50ns 5v figure 28. inverting large signal pulse response, r l = 1 k w 10 90 100 0% 200mv 50ns 200mv figure 29. inverting small signal pulse response, r l = 1 k w
ad817 rev. b C9C driving capacitive loads the internal compensation of the ad817, together with its high output current drive, permit excellent large signal performance while driving extremely high capacitive loads. c l 1000pf r in 1k w +v s tektronix p6201 fet probe hp pulse generator 50 w 1k w v out 0.01 m f 3.3 m f ? s v in tektronix 7a24 pr eamp ad817 7 6 3 2 4 0.01 m f 3.3 m f figure 30a. inverting amplifier driving a 1000 pf capacitive load 10 90 100 0% 5v 500ns 5v 100pf 1000pf figure 30b. inverting amplifier pulse response while driving capacitive loads theory of operation the ad817 is a low cost, wide band, high performance opera- tional amplifier which effectively drives heavy capacitive or resis- tive loads. it also provides a constant slew rate, bandwidth and settling time over its entire specified temperature range. the ad817 (figure 31) consists of a degenerated npn differ- ential pair driving matched pnps in a folded-cascode gain stage. the output buffer stage employs emitter followers in a class ab amplifier which delivers the necessary current to the load while maintaining low levels of distortion. the capacitor, c f , in the output stage mitigates the effect of capacitive loads. at low frequencies, and with low capacitive loads, the gain from the compensation node to the output is very close to unity. in this case, c f is bootstrapped and does not contribute to the ov erall compensation capacitance of the de vice. as the capacitive load is increased, a pole is formed with the output impedance of the output stage. this reduces the gain, and therefore, c f is incompletely bootstrapped. effectively, some fraction of c f contributes to the overall compensation capacitance, reducing the unity gain bandwidth. as the load capacitance is further increased, the bandwidth continues to fall, maintaining the stability of the amplifier. c f ?n +in null 1 null 8 output +v s ? s figure 31. simplified schematic input considerations an input protection resistor (r in in figure 22) is required in cir- cuits where the input to the ad817 will be subjected to tran- sient or continuous overload voltages exceeding the +6 v maximum differential limit. this resistor provides protection for the input transistors by limiting their maximum base current. for high performance circuits, it is recommended that a bal- ancing resistor be used to reduce the offset errors caused by bias current flowing through the input and feedback resistors. the balancing resistor equals the parallel combination of r in and r f and thus provides a matched impedance at each input terminal. the offset voltage error will then be reduced by more than an order of magnitude. grounding & bypassing when designing high frequency circuits, some special precau- tions are in order. circuits must be built with short interconnect leads. when wiring components, care should be taken to pro- vide a low resistance, low inductance path to ground. sockets should be avoided, since their increased interlead capacitance can degrade circuit bandwidth. feedback resistors should be of low enough value (<1 k w ) to assure that the time constant formed with the inherent stray capacitance at the amplifiers summing junction will not limit performance. this parasitic capacitance, along with the parallel resistance of r f /r in , form a pole in the loop transmission which may result in peaking. a small capacitance (1 pfC5 pf) may be used in parallel w ith the feedback resistor to neutralize this effect. power supply leads should be bypassed to ground as close as possible to the amplifier pins. ceramic disc capacitors of 0.1 m f are recommended. +v s 10k w ? s ad817 7 3 2 4 8 6 1 v os adjust figure 32. offset null configuration
rev. b C10C ad817 offset nulling the input offset voltage of the ad817 is inherently very low. however, if additional nulling is required, the circuit shown in figure 32 can be used. the null range of the ad817 in this con- figuration is 15 mv. ad817 settling time settling time is comprised primarily of two regions. the first is the slew time in which the amplifier is overdriven, where the output voltage rate of change is at its maximum. the second is the linear time period required for the amplifier to settle to within a specified percent of the final value. 0.10 0.20 0.15 0.05 0.05 0 0 4 6 10 8 2 0 350 400 300 250 200 150 100 50 settling time to % of final value output swing ?volts figure 33. settling time in ns 0 v to +10 v measuring the rapid settling time of ad817 (45 ns to 0.1% and 70 ns to 0.01%C10 v step) requires applying an input pulse with a very fast edge and an extremely flat top. with the ad817 con- figured in a gain of C1, a clamped false summing junction re- sponds when the output error is within the sum of two diode voltages (a1 volt). the signal is then amplified 20 times by a clamped amplifier whose output is connected directly to a sam- pling oscilloscope. figures 33 and 34 show the settling time of the ad817, with a 10 volt step applied. 0.05 0.05 0 0.20 0.10 0.15 ?0 ? ? 0 ? ? 0 350 400 300 250 200 150 100 50 settling time to % of final value output swing ?volts figure 34. settling time in ns 0 v to C10 v ad829 100 w 0.47 m f 0.01 m f +v s 0.47 m f 0.01 m f ? s short, direct connection to tektronix type 11402 oscilloscope preamp input section settling output 2 hp2835 error amplifier v error output 10 2 hp2835 1.9k w 100 w ad817 0.01 m f +v s 0.01 m f 2.2 m f ? s 2.2 m f 10pf scope probe capacitance tektronix p6201 fet probe to tektronix type 11402 oscilloscope preamp input section 500 w 5?8pf device under test note: use circuit board with ground plane false summing node null adjust 1k w 100 w 1k w 50 w coax cable ttl level signal generator 50hz output 7, 8 0 to 10v power supply ei&s dl1a05gm mercury relay error signal output 500 w 50 w 6 3 2 4 15pf 1m w 7 6 3 2 4 5 13 2 1, 14 digital ground analog ground 7 figure 35. settling time test circuit
ad817 rev. b C11C a high performance adc input buffer high performance analog to digital converters (adcs) require input buffers with correspondingly high bandwidths and very low levels of distortion. typical requirements include distortion levels of C60 db to C70 db for a 1 volt p-p signal and band- widths of 10 mhz or more. in addition, an adc buffer may need to drive very large capacitive loads. the circuit of figure 36 is useful for driving high speed convert- ers such as the differential input of the ad733, 10-bit adc. this circuit may be used with other converters with only minor modifications. using the ad817 provides the user with the op- tion of either operating the buffer in differential mode or from a single +5 volt supply. operating from a +5 volt power supply helps to avoid overdriving the adca common problem with buffers operating at higher supply voltages. single supply operation another exciting feature of the ad817 is its ability to perform well in a single supply configuration. the ad817 is ideally suited for applications that require low power dissipation and high output current and those which need to drive large capaci- tive loads, such as high speed buffering and instrumentation. referring to figure 37, careful consideration should be given to the proper selection of component values. the choices for this particular circuit are: r1+ r3//r2 combine with c1 to form a low frequency corner of approximately 300 hz. r2 10k w c3 0.1 m f r1 9k w r3 1k w c2 0.1 m f c1 0. 1 m f c l 20 0p f r l 15 0 w select c1, r1, r2 & r3 for desired low frequency corner. (r2 = r1 + r3) c out +v s v out v in ad817 7 6 3 2 4 0.01 m f 3.3 m f figure 37. single supply amplifier configuration combining r3 with c2 forms a low-pass filter with a corner frequency of 1.5 khz. this is needed to maintain amplifier psrr, since the supply is connected to v in through the input divider. the values for r l and c l were chosen to demonstrate the ad817s exceptional output drive capability. in this con- figuration, the output is centered around 2.5 v. in order to eliminate the static dc current associated with this level, c3 was inserted in series with r l . 52.5 w 0.1 m f 1k w 0.1 m f ? s 1k w 1k w 1k w ad773 10 -bit 18mhz adc v ina v inb adref43 voltage reference +2.5v 50 w coax cable v in 500mvp-p max +v s ad817 7 6 3 2 4 26 27 0.1 m f 0.1 m f ? s +v s ad817 7 6 3 2 4 +5v common ?v 100 m f 25v 100 m f 25v +v s ? s figure 36. a differential input buffer for high bandwidth adcs
rev. b C12C ad817 high speed dac buffer the wide bandwidth and fast settling time of the ad817 make it a very good output buffer for high speed current output d/a converters like the ad668. as shown in figure 38, the op amp establishes a summing node at ground for the dac output. the output voltage is determined by the amplifiers feedback resistor (10.24 v for a 1 k w resistor). note that since the dac gener- ates a positive current to ground, the voltage at the amplifier output will be negative. a 100 w series resistor between the noninverting amplifier input and ground minimizes the offset effects of op amp input bias currents. 1 2 3 7 24 23 22 18 8 9 10 17 16 15 11 12 14 13 4 5 21 20 6 19 ad668 +15v 10 m f to analog ground plane 0.1 m f 1v nominal reference input 10k w 1k w 100 w ad817 analog ground plane analog output analog supply ground 0.1 m f 10 m f ?5v +5v 1k w 100pf digital inputs msb lsb v refcom refin1 refin2 r acom lcom ibpo v thcom vth ee load out cc i figure 38. high speed dac buffer outline dimensions dimensions shown in inches and (mm). 8-pin plastic mini-dip (n-8) 0.011 0.003 (0.28 0.08) 0.30 (7.62) ref 15 0 pin 1 4 5 8 1 0.25 (6.35) 0.31 (7.87) 0.10 (2.54) bsc seating plane 0.035 0.01 (0.89 0.25) 0.18 0.03 (4.57 0.76) 0.033 (0.84) nom 0.018 0.003 (0.46 0.08) 0.125 (3.18) min 0.165 0.01 (4.19 0.25) 0.39 (9.91) max 8-pin soic (so-8) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 pin 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 4 5 1 8 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.1968 (5.00) 0.1890 (4.80) c1707bC5C6/95 printed in u.s.a.

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